David W. Wall
dr.david.wall@gmail.com
Objective
I have extensive experience in writing compilers,
performance tools, and architecture simulation, and I'm a
good writer and speaker. I like to get insight into a big
hard problem by finding helpful solutions to smaller problems
and then building from there.
Education
BS in mathematics 1974, University of New Mexico
MS in computer science 1978, Stanford University
PhD in computer science 1980, Stanford University
Experience
David Wall Consulting.
Member of Technical Staff
Writing, programming, scripting, critiquing.
Apple.
Senior Systems Software Engineer, 2013-2015.
Infrastructure and architectural/compiler analysis for Macroscalar.
Google.
Member of Technical Staff, 2008-2011.
Worked on tools for monitoring and analyzing the performance of
distributed software.
Transmeta Corporation.
Principal Engineer, 2001-2007.
Member of Technical Staff, 1997-2001.
Designed, built, and maintained integrated tools for monitoring
the performance of Transmeta's code-morphing system. I also
wrote simulation models for hardware branch predictors and
prefetchers.
Silicon Graphics.
Member of Technical Staff, 1995-1996.
Architectural simulation and performance modelling.
Digital Equipment Corporation Western Research Laboratory.
Consulting Engineer, 1988-1995.
Principal Engineer, 1983-1988.
Wrote common backend and link-time register allocator
for WRL's Titan compilers, and used this framework
to do a wide range of research in compilers, profiling,
and computer architectural performance.
The Pennsylvania State University.
Assistant professor of computer science, 1980-1983.
Taught intro architecture, programming languages,
compiler construction, and concurrent programming.
References
Available on request.
Selected publications
(A full publication list is available
here.)
-
Mechanisms
for Broadcast and Selective Broadcast.
PhD thesis, Stanford University, June 1980.
Technical Report 190, Computer Systems Laboratory,
Stanford University, 1980.
-
Messages as active
agents. Ninth Annual ACM Symposium on Principles of Programming Languages,
January 1982, pages 34-39.
-
Global register allocation at link-time.
Proceedings of the SIGPLAN '86 Symposium on Compiler Construction,
June 1986, pp. 264-275.
Also available as WRL Research Report 86/3.
-
The Mahler experience: Using an intermediate language as the machine
description.
With Michael L. Powell.
Second International Symposium on Architectural Support for
Programming Languages and Operating Systems, October 1987, pages
100-104.
A more detailed version is available as WRL Research Report 87/1.
-
Register windows vs. register allocation.
Proceedings of the SIGPLAN '88 Conference on Programming Language
Design and Implementation, June 1988, pages 67-78.
Also available as WRL Research Report 87/5.
-
Available instruction-level parallelism for superscalar and
superpipelined machines.
With Norman P. Jouppi.
Third International Symposium on Architectural Support for
Programming Languages and Operating Systems, April 1989,
pages 272-282.
Also available as WRL Research Report 89/7.
Reprinted in David J. Lilja, Architectural Alternatives
for Exploiting Parallelism, IEEE Computer Society Press,
1991.
-
Long address traces from RISC machines: Generation and analysis.
With Anita Borg and R. E. Kessler.
Seventeenth Annual International Symposium on Computer
Architecture, May 1990, pages 270-279.
A more detailed version is available as WRL Research Report 89/14.
-
Limits of instruction-level parallelism.
Fourth International Symposium on Architectural Support for
Programming Languages and Operating Systems, April 1991, pages
176-188.
Also available as WRL Technical Note TN-15.
Reprinted in David J. Lilja,
Architectural Alternatives for Exploiting Parallelism,
IEEE Computer Society Press, 1991.
- This paper received the "Most Influential Paper Award" 25 years later
at ASPLOS 2016.
-
Predicting program behavior using real or estimated profiles.
Proceedings of the SIGPLAN '91 Conference on Programming
Language Design and Implementation, June 1991, pages 59-70.
Also available as WRL Technical Note TN-18.
-
Experience with a software-defined machine architecture.
ACM Transactions on Programming
Languages and Systems 14(3),
pp. 299-338, July 1992.
Also available as WRL Research Report 91/10, August 1991.
-
A practical system for intermodule code optimization at link-time.
With Amitabh Srivastava.
Journal of Programming Languages 1(1),
pp. 1-18, March 1993.
Also available as WRL Research Report 92/6, December 1992.
-
Link-time optimization of address calculation on a 64-bit architecture.
With Amitabh Srivastava.
Proceedings of the SIGPLAN '94 Conference on
Programming Language Design and Implementation,
pp. 49-60, June 1994.
Also available as WRL Research Report 94/1, February 1994.
Patents
-
Method for quickly acquiring and using very long traces of mixed system and user
memory references.
With Anita Borg. U.S. Patent number
5,274,811.
Granted 28 December 1993.
Other professional activities
-
Member of program committee for the Twelfth Annual ACM Symposium
on Principles of Programming Languages, January 1985.
-
Member of program committee for SIGPLAN Conference on Programming
Language Design and Implementation: 1990, 1992, 1993 (program
chair), 1995 (general chair), 1999.
-
Member of program committee for Seventh International Conference on
Architectural Support for Programming Languages and Operating
Systems, 1996.
-
Invited faculty for the ACM/MAA Institute for Retraining in
Computer Science, 1983, 1984, 1986, 1987.
-
Invited participant at the CODE '91 International Workshop on
Code Generation, May 1991. Presented two talks: "Systems
for Late Code Modification" and "Experience with a Software
Architecture."
-
Invited panelist for "Five Instructions Per Clock: Truth or
Consequences" at Hot Chips Symposium III, August 1991.
-
Tutorial speaker on "Post-Compiler Code Transformation" at
SIGPLAN '92 Conference on Programming Language Design
and Implementation, June 1992.
-
Invited participant at the Workshop on the Future of Research in
Programming Languages and Compilers, sponsored by NSF, January
1993.
-
Invited participant at IFIP Working Group 2.4 (Systems Implementation
Languages), October 1993.
-
Member at Large of the SIGPLAN Executive Committee, July 1993 to
June 1995.